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The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis that is based on statistical bounds of the circuit delay. Since these bounds havedoi:10.1145/775832.775922 dblp:conf/dac/AgarwalBZV03 fatcat:h6kx327wlfgzzbnp5cunzk76nm