Computation and Refinement of Statistical Bounds on Circuit Delay

Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma Vrudhula
2003 Proceedings of the 40th conference on Design automation - DAC '03  
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis that is based on statistical bounds of the circuit delay. Since these bounds have
more » ... e these bounds have linear run time complexity with circuit size, they can be computed efficiently for large circuits. Since both a lower and upper bound on the true statistical delay is available, the quality of the bounds can be determined. If the computed bounds are not sufficiently close to each other, we propose a heuristic to iteratively improve the bounds using selective enumeration of the sample space with additional run time. We demonstrate that the proposed bounds have only a small error and that by carefully selecting an small set of nodes for enumeration, this error can be further improved.
doi:10.1145/775832.775922 dblp:conf/dac/AgarwalBZV03 fatcat:h6kx327wlfgzzbnp5cunzk76nm