An experimental evaluation of real-time DVFS scheduling algorithms

Sonal Saha, Binoy Ravindran
2012 Proceedings of the 5th Annual International Systems and Storage Conference on - SYSTOR '12  
We implement and experimentally evaluate the timeliness and energy consumption behaviors of fourteen state-of-the-art Real-Time Dynamic Voltage and Frequency Scaling (RT-DVFS) schedulers on two hardware platforms. The schedulers include CC-EDF, LA-EDF, REUA, DRA, and AGR1, among others, and the hardware platforms include the Intel i5 processor and the AMD Zacate processor. We implemented the schedulers in a real-time Linux kernel and measured their timeliness and energy consumption under a
more » ... of workloads including CPU-intensive, memory-intensive, mutual exclusion lock-intensive, and processor-underloaded and overloaded workloads. Our studies reveal that measuring the CPU power consumption as the cube of CPU frequency -as often done in the simulation-based RT-DVFS literature -ignores the idle state CPU power consumption, which is orders of magnitude smaller than the active power consumption. Consequently, power savings obtained by optimizing active power (i.e., RT-DVFS) is offset by completing tasks sooner by running at high frequency and quickly transitioning to the idle state (i.e., no DVFS). Thus, the active power consumption savings of the RT-DVFS techniques' revealed by our measurements are orders of magnitude smaller than their simulation-based savings reported in the literature.
doi:10.1145/2367589.2367604 dblp:conf/systor/SahaR12 fatcat:p44bnlekp5dhjhhzvyc3nkun3q