A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is
International Journal of New Trends in Electronics and Communication
Design of area-and power-efficient high-speed data path logic systems forms the largest areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is span for reducing the area and power consumption in the CSLA. Thisfatcat:sy46s7vwyjcy7cpqnjzqjkgjdi