System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs

Sumeet S. Kumar, Arnica Aggarwal, Radhika Sanjeev Jagtap, Amir Zjajo, Rene van Leuken
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Modern 3-D multiprocessor systems-on-chip (MP-SoC) incorporate processing elements (PEs) and memories within die-stacks interconnected using through-silicon vias (TSVs). The resulting power density of these systems necessitates the inclusion of thermal effects in the architecture space exploration stage of the design process. The number and placement of TSVs influences the thermal conductivity in the vertical direction in die-stacks, and consequently these must be considered during thermal
more » ... sis. However, the special requirement of keep out zones (KOZs) for TSVs due to mechanical stress considerations complicates the design of the vertical interconnect, potentially impacting its electrical performance as well. This paper presents an integrated methodology that allows for TSV topology exploration to evaluate the best vertical interconnect structure while considering crosstalk, area overheads, and KOZ requirements using an initial system floorplan. After incorporating feedback from the exploration, the resulting vertical interconnect is included within a temperature-power simulation that estimates the thermal profile of the 3-D stack. Within this methodology, a novel power management scheme for 3-D MP-SoCs that considers both temperature as well as positional information and thermal relationships between PEs, while performing dynamic voltage-frequency scaling (DVFS), is introduced. The scheme effectively maintains smooth temperature profiles, decreases fluctuations in voltage-frequency levels, and increases the aggregate frequency of operation at a lower total power dissipation. Further, the scheme is applied to a stack partitioned into voltage islands, where it is shown to match the conventional per-core DVFS schemes in its performance. Index Terms-3-D integrated circuits, design methodology, system-level design, thermal management, through-silicon vias (TSVs). Sumeet S. Kumar (S'08) received the B.E. degree in electronics and communications engineering from Visvesvaraya Technological University, Belgaum, India, in 2008, and the M.Sc. degree in electrical engineering with a specialization in microelectronics from the Delft University of Technology, Delft, The Netherlands, in 2010, where he is currently pursuing the Ph.D. degree in electrical engineering with the Circuits and Systems Group. He was an Intern with Indrion Technologies, Bangalore, India, in 2008, where he worked on developing energy-efficient instruction set extensions for a sensor control network processor. His work focuses on the design of a high-performance 3-D manycore processor architecture that is scalable, dependable, and easy to program. Arnica Aggarwal received the B.Tech. degree in electronics and communication engineering from the Amity School of Engineering and Technology, Noida, India, in 2009, and the M.Sc. degree in electrical engineering with a specialization in microelectronics from the The Netherlands, in 2012, and is currently an E-Integrator with the Electronics Development Department. Her current research interests include VLSI design, power aware and low power, and energy digital system design. Radhika Sanjeev Jagtap received the B.Tech. degree in electronics and telecommunication engineering from the College of Engineering, Pune, India, in 2007, and the M.Sc. degree in electrical engineering with a specialization in microelectronics from the
doi:10.1109/tvlsi.2013.2273003 fatcat:mlpcivb3pbh67g6ohulcmpv3ze