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0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file
1992
IEEE Journal of Solid-State Circuits
Preserved Fulltext
BiCMOS standard cell macros, includiug a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kilobyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0,1-W 3-ns adder, are designed with a 0.5-pm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several Bi-CMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip.
doi:10.1109/4.165339
fatcat:ty2jhb7avnha3jkvq4xovfjnhi