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Logic synthesis of multilevel circuits with concurrent error detection
1997
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
This paper presents a procedure for synthesizing multilevel circuits with concurrent error detection. All errors caused by single stuckat faults are detected using a parity-check code. The synthesis procedure (implemented in Stanford CRC's TOPS synthesis system) fully automates the design process, and reduces the cost of concurrent error detection compared with previous methods. An algorithm for selecting a good parity-check code for encoding the circuit outputs is described. Once the code has
doi:10.1109/43.644041
fatcat:fy7oczajonb27pufiwak4ptl5a