Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

M. Irfan Uddin, Chris R. Jesshope, Michiel W. van Tol, Raphael Poss
2012 Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation Methods and Tools - RAPIDO '12  
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores Irfan-Ud-Din, M.; Jesshope, C.R.; van Tol, M.W.; Poss, R.C. ABSTRACT The current many-core architectures are generally evaluated by a detailed emulation with a cycle-accurate simulation of the execution time. However this detailed simulation of the architecture makes the evaluation of large programs very slow. Since the focus in many-core architecture is shifting from the performance of the
more » ... al core to the overall behavior of chip, high-level simulations are becoming necessary, which evaluate the same architecture at less detailed level and allow the designer to make quick and reasonably accurate design decisions. We have developed a high-level simulator for the design space exploration of the Microgrid, which is a many-core architecture comprised of many finegrained multi-threaded cores. This simulator allows us to investigate mapping and scheduling strategies of families (i.e. groups of threads) in developing an operating environment for the Microgrid. The previous method to evaluate the workload counted in basic blocks was inaccurate. The key problem is that with many concurrent threads the latency of certain instructions are hidden because of the multithreaded nature of the core. This paper presents a technique to manage the execution time of different types of instructions with thread concurrency. We believe to achieve high accuracy in evaluating programs in the high-level simulator.
doi:10.1145/2162131.2162132 dblp:conf/rapido/UddinJTP12 fatcat:ylakm5gbfngazf4ngr7jcy3dfe