Physical planning for the architectural exploration of large-scale chip multiprocessors

Javier de San Pedro, Nikita Nikitin, Jordi Cortadella, Jordi Petit
2013 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)  
This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout constraints that enforce regularity in the interconnect networks. Routing is performed on top of memories and components that underutilize the available metal layers for interconnectivity. The experiments demonstrate the impact of physical parameters in the selection of the
more » ... ost efficient architectures. Thus, the integrated flow contributes to deliver physically-viable architectures and simplify the complex design closure of large-scale CMPs. N E S W Fig. 4. Final floorplan with wire planning information
doi:10.1109/nocs.2013.6558399 dblp:conf/nocs/PedroNCP13 fatcat:fkavtl2kanezbdqh5gb3yknki4