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Interfacing a high speed crypto accelerator to an embedded CPU
Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004.
Crypto co-processors are needed for acceleration of encryption functions. But critical to the performance gain is the selection of an adequate interface. This paper presents the AES acceleration for two interface options to the LEON CPU core: the CPI interface and the memorymapped interface. The complete system including the LEON core and the loosely coupled AES accelerators are implemented on an FPGA and the software programs that control the AES accelerators are tested. The cycle count, thedoi:10.1109/acssc.2004.1399180 fatcat:efvf3t2y4be4zi5w7ydtvoe4wq