The development of high performance FFT IP cores through hybrid low power algorithmic methodology

Wei Han, A. T. Erdogan, T. Arslan, M. Hasan
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
This paper presents a solution based on parallel-pipelined architectures for high throughput and power efficient FFT IP cores. Low power consumption can be gained through the combination of hybrid low power algorithms and architectures. A number of IP cores have been implemented for the comparison of the impact of parameterization on power/area/speed performance. The results show that up to 55% and 52% power saving can be achieved by the combination of the above techniques for 64-point
more » ... r 64-point 4-parallel-pipelined FFT and 16-point 2-parallel-pipelined FFT respectively, as compared to R4SDC pipelined FFTs.
doi:10.1145/1120725.1120959 dblp:conf/aspdac/HanEAH05 fatcat:r5niwo77zfe2xcubcipyjtghei