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A new interpolation technique for time interleaved $$\Upsigma\Updelta$$ A/D converters
<span title="2011-07-29">2011</span>
<i title="Springer Nature">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rers662hkvfkldrprmugqsdxly" style="color: black;">Analog Integrated Circuits and Signal Processing</a>
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Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra
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... es instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance. The proposed technique was simulated and implemented in a four channel time interleaved sigma-delta designed in a 1.2 V 65 nm CMOS process.
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