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ASIC implementation of random number generators using SR latches and its evaluation
2016
EURASIP Journal on Information Security
A true random number generator (TRNG) is proposed and evaluated by field-programmable gate arrays (FPGA) implementation that generates random numbers by exclusive-ORing (XORing) the outputs of many SR latches (Hata and Ichikawa, IEICE Trans. Inf. Syst. E95-D(2): [426][427][428][429][430][431][432][433][434][435][436] 2012). This enables compact implementation and generates high-entropy random numbers. In this paper, we fabricate and evaluate 39 TRNGs using SR latches on 0.18 μm ASICs. Random
doi:10.1186/s13635-016-0036-1
fatcat:2hwua6envfbfrluk46da5ujjpe