Power supply ramping for quasi-static testing of PLLs

J. Pineda de Gyvez, G. Gronthoud, C. Cenci, M. Posch, T. Burger, M. Koller
2004 International Conferce on Test  
An innovative approach for testing PLLs in open loopmode is presented. Tbe operational method consists of ramping the PLL's power supply by means of a periodic sawtooth signal. The reference and feedback inputs of the PLL in open-loop mode are connected to the clock reference signal or to ground. Then, the corresponding quiescent current, clock output, and oscillator control voltage signatures are monitored and sampled at specific times. When the power supply is swept, all transistors are
more » ... into various regions of operation causing the sensitivity of the fads to the specific stimulus to be magnified. The developed method of structural testing for PLLs yields high fault coverage results making it a potential and attractive technique for production wafer testing.
doi:10.1109/test.2004.1387363 dblp:conf/itc/GyvezGCPBK04 fatcat:lyxxt7nvc5fzjo5gw5x6tkya6q