A Scheduling Algorithm for Asymmetric Processor Architecture

S. Subha
2010 International Journal of Computer Applications  
Chip multiprocessors are used widely today. The cores in a chip can be homogeneous or heterogeneous. This paper proposes a scheduling algorithm for heterogeneous multiprocessors wotj, multiple functional units of varying speed in each processor. Instructions that can be scheduled in parallel are considered. An optimization function is developed to allocate the processes to the processors that minimize the overall execution time. The proposed model is simulated for a chosen example and verified to give 46% improvement in performance.
doi:10.5120/1623-2182 fatcat:pjs63n3xqnbzlddayh4vp3ep3m