Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
This paper introduces a new approach for minimizing power dissipation on the memory address bus. The proposed approach relies on the availability of smart memories that have certain awareness of the instruction format of one or more architectures. Based on this knowledge, the memory calculates or predicts the instruction and data addresses. Hence, not all addresses are sent from the processor to the memory. This, in turn, significantly reduces the activity on the memory bus. The proposed method
more » ... can eliminate up to 97% of the transitions on the instruction address bus and 75% of the transitions on the data address bus with a small hardware overhead. The actual power savings of 85% for the instruction bus and 64% for the data bus were achieved for a per-line bus capacitance of 10pF. 2 Some fast growing category of applications, in which on-chip caches are not used, are the stream processing and network processing. Using a cache does not help to increase the performance for these applications.
doi:10.1145/1119772.1119774 dblp:conf/aspdac/AghaghiriFP03 fatcat:nj4zfe3lsbembfkdlcw2rjchn4