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This paper introduces a new approach for minimizing power dissipation on the memory address bus. The proposed approach relies on the availability of smart memories that have certain awareness of the instruction format of one or more architectures. Based on this knowledge, the memory calculates or predicts the instruction and data addresses. Hence, not all addresses are sent from the processor to the memory. This, in turn, significantly reduces the activity on the memory bus. The proposed methoddoi:10.1145/1119772.1119774 dblp:conf/aspdac/AghaghiriFP03 fatcat:nj4zfe3lsbembfkdlcw2rjchn4