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ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)
This paper presents a new high-speed logic circuit family based on an interdigitated array structure for deep sub-micron IC design. The circuit family consists of a comparator, a priority encoder, and an incrementor for 128-bit data processing. The proposed circuit includes three schemes: 1) a divided column scheme, 2) a programmable sense-amplifier activation scheme, and 3) an interdigitated column scheme. These schemes achieved a 22.2% delay reduction and a 37.5% chip area reduction over thedoi:10.1109/esscirc.2003.1257104 fatcat:klp4pqdlunhczokaamvu2czjv4