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In this paper, technology mapping algorithms for minimizing power consumption in FPGA design are studied. The technology mapping problem for power minimization has been shown to be NP-complete. Furthermore, there are other important objectives, such as the number of PLBs Programmable Logic Blocks, the number of levels and so on, that should also be optimized simultaneously. W e propose a transformational approach in which w e start with a mapping solution which optimizes certain objectivesdoi:10.1145/266021.266312 dblp:conf/dac/ChenHL97 fatcat:7kwyjxit4fdqnd6d63gpsk5uxm