In this paper, technology mapping algorithms for minimizing power consumption in FPGA design are studied. The technology mapping problem for power minimization has been shown to be NP-complete. Furthermore, there are other important objectives, such as the number of PLBs Programmable Logic Blocks, the number of levels and so on, that should also be optimized simultaneously. W e propose a transformational approach in which w e start with a mapping solution which optimizes certain objectives

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... the number of PLBs. The mapping solution is then transformed to reduce the power consumption while keeping the number of PLBs xed. Our algorithm explores the possibilities of transforming the functionality of the PLBs so that the switching densities of the output edges of the PLBs will be reduced, leading to a reduction in total power consumption. Our transformational approach can also be viewed as a re-engineering approach in which p o w er reduction is achieved through re-routing after the PLBs have been placed, utilizing e ectively the capability of a PLB to realize any boolean function of up to k variables.