A reconfigurable parallel signature analyzer for concurrent error correction in DRAM

P. Mazumder, J.H. Patel, J.A. Abraham
1990 IEEE Journal of Solid-State Circuits  
An efficient strategy to utilize a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAM'S is described. For a two-level w-bit, n-word memory system, the proposed technique needs only one additional chip as opposed to log, w + 2 in the conventional Hamming code. Such an error-correction circuit (ECC) significantly improves the reliability of the memory system. Abstract -This correspondence presents ganged-CMOS logic (GCMOS), a technique employing CMOS inverters with
more » ... r outputs shorted together, driving one or more encoding inverters. These encoding inverters, serving to quantize the nonbinary signal at the "ganged" node, effectively buffer it from external circuitry, thus allowing locally smaller noise margins. As demonstrated by two novel adders, GCMOS achieves higher speeds and lower input capacitances than static CMOS, at the expense of higher static power dissipation.
doi:10.1109/4.102687 fatcat:pc2ki7ple5asrfhjzuskw7e44a