Throughput Testbench Setup Development For Memory Expansion Of Gensets

Lokesh Khandare, Rathod D P
In power generation industry, there is a huge demand regarding variation of Customer requirements/ feedback which needs of developing and modifying the software scripts. Adding Genset functions in software script causes Genset memory capacity on brink and it will be insufficient to add more smart functions to the Genset. Therefore in order to suffice the latest market needs, memory expansion is vital for the legitimate performance of the Genset. Further these causes heavy load on the framework
more » ... f a Genset function and thus increases the execution time which may decline the performance of the Genset. This paper describes about the implementation of external memory and the intense approach reducing the execution time with the help of Throughput test setup. Hardware-in-the-loop (HIL) testing approach in the design of power electronics i.e. throughput setup is used which gives the real time simulation environment. Moreover, the setup interprets the particular task in a framework having overload task affecting the performance.In addition, generate the Throughput log of Memory expanded Genset boards in the database system for comparison and use it to correlate with existing Genset boards to review the "unskipped frame" for achieving the goal of zero failure. Thus, obtaining the lower Throughput value eventually reduces the execution time for consistent behavior of Gensets. Finally, the canny way of Throughput testing for Memory Expansion of Genset is summarized here. When the processor is turned on, the system is booted from the external Flash to Gensets external SRAM. As soon as a command is received to the processor, the required function is loaded into the SRAM from the flash i.e. Memory management for calculation depends on the Chip select line w.r.t. the priority of the tasks and the time required for execution. External Flash used in the hardware setup is a parallel NOR flash which has a faster Read operation rather than NAND flash having high Write and Erase speed. The execution time of the command is the propagation delay i.e. the time required by the processor for fetching the data from the External SRAM. Analysing the root cause of these fault code and troubleshooting should be done for proper functioning of Genset and initialization of the test. Ultimately, checking the Utility of Modbus register and obtaining the throughput values. If the throughput value obtained is more than the desired throughput range, then software scripts should be modified. These updated scripts should be calibrated on the Gensets boards and the throughput testing should be processed again. Here, figure-6 shows the test report sheet obtained from the Monitoring tool after simulation. The throughput value obtained in this test is 56%. V. CONCLUSION This paper depicts about the development of Throughput testbench setup, its implementation and Simulation. The aim for development of this testbench is to achieve the Throughput value in the desired range of 50-60% for Memory Expanded Genset board is achieved by making the "umskippedFrame" value to zero. Thus the desired Throughput value suffices the markets needs i.e. advanced features required by the users for the better performance of the gensets. Moreover, on achieving the desired throughput range, the board will be capable of adding extensive advance features.
doi:10.17148/ijireeice.2017.5530 fatcat:lxfhp3ggxzfidc7dxmco7p2mdm