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A Domain Extension Algorithm for Digital Error Correction of Pipeline ADCs
2014
Circuits and Systems
A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises significant improvements to the spurious-free dynamic range (SFDR), the total harmonic distortion (THD), the
doi:10.4236/cs.2014.52006
fatcat:lx5fthga55btvmqucjrrcpzzym