Design of 1 63 Level Inverter Using 9 Switches for Harmonics Mitigation

P.I.D.T. Baladuraikannan, D. Pandiaraj, B.M. Kesavi, S. Monikka
2020 Zenodo  
This project proposes a 1f 63 level inverter with 9 switches only, with a novel pulse width-modulated (PWM) control scheme. In this 63 Level inverter output voltage level increasing by using nine numbers of switches driven by the switch ON/OFF modulation techniques. The inverter is capable of producing sixty three levels of output-voltage (During half positive cycle voltage increase from 0V to +Vdc & decreases to 0V. During negative half cycle voltage decreases from 0V to -Vdc & increases to
more » ... c & increases to 0V) from the dc supply voltage. This topology reduces the THD with less number of switches. The H bridge circuit with multiplier cell produces the sixty three level output voltage waveform. The proposed system was verified through MATLAB simulation and the hardware is implemented by using DSPIC30F2010 controller.
doi:10.5281/zenodo.3833704 fatcat:nhzvczlobbfazedq27w3dpkgwy