Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems [chapter]

Manel Ammar, Mouna Baklouti, Maxime Pelcat, Karol Desnos, Mohamed Abid
2015 Studies in Computational Intelligence  
Massively Parallel Multi-Processors System-on-Chip (MP2SoC) architectures require efficient programming models and tools to deal with the massive parallelism present within the architecture. In this paper, we propose a tool which automates the generation of the System-Level Architecture Model (S-LAM) from a Unified Modeling Language-based (UML) model annotated with the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) profile. The S-LAMbased description of the MP2SoC architecture
more » ... s conformed to the IP-XACT standard. The integration of our generator within a co-design framework provides the specification of the whole MP2SoC system using UML and MARTE. Then, gradual refinements allow the execution of a rapid prototyping process. Recent trends in High-Performance Computing (HPC) architectures show that, due to the end of processor frequency scaling, performance increases are mostly gained by employing more processor cores [1]. This trend draws attention to the effectiveness of Massively Parallel Multi-Processors System-on-Chip (MP2SoC) architectures in the HPC domain. Designers of high performance MP2SoC are facing many critical design challenges including: PE PE PE PE PE PE PE PE M M M M M M M M Local network Global network Cluster1 PE M
doi:10.1007/978-3-319-23509-7_14 fatcat:vaiwdsuhuvcejjuw6bptlw3jwu