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Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
[article]
2019
arXiv
pre-print
Approximate Logic Synthesis (ALS) is the process of synthesizing and mapping a given Boolean network to a library of logic cells so that the magnitude/rate of error between outputs of the approximate and initial (exact) Boolean netlists is bounded from above by a predetermined total error threshold. In this paper, we present Q-ALS, a novel framework for ALS with focus on the technology mapping phase. Q-ALS incorporates reinforcement learning and utilizes Boolean difference calculus to estimate
arXiv:1902.00478v1
fatcat:oa323icxcvft5kpnalzzahwqzu