Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors

Hsiao-Yi Lin, Chun-Yen Chang, Tan Fu Lei, Feng-Ming Liu, Wen-Luh Yang, Juing-Yi Cheng, Hua-Chou Tseng, Liang-Po Chen
1996 IEEE Electron Device Letters  
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (5550 C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHVICVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3
more » ... lectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step is not needed. A field effect mobility of 46 cm2N-s, ON/OFF current ratio of over lo7, and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
doi:10.1109/55.541762 fatcat:hsrbuhykj5awno2ojlubvhrpgi