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Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems
2012
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design - ISLPED '12
Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve the NoC efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU
doi:10.1145/2333660.2333675
dblp:conf/islped/YinZHSZ12
fatcat:rpivyktfdjbyfar3hindo4n7cy