Device optimization for ultra-low power digital sub-threshold operation

Bipul C. Paul, Arijit Raychowdhury, Kaushik Roy
2004 Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04  
Digital circuits operated in the sub-threshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultra-low power and medium frequency of operation. It is possible to implement sub-threshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, a Si MOSFET so optimized for performance in the
more » ... ormance in the super-threshold regime is not the best device to use in the sub-threshold domain. In this paper, we propose device designs apt for sub-threshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the sub-threshold region.
doi:10.1145/1013235.1013266 dblp:conf/islped/PaulRR04 fatcat:swtbpbj6vbeujlvzo7qyucbfby