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Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis
2007
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and
doi:10.1093/ietfec/e90-a.4.875
fatcat:nw2gqiwlrbf2vcmev6fmp3qncu