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Partial core encryption for performance-efficient test of SOCs
2003
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
The isolation of a core through full I/O scan helps ease SOC test challenges; yet the performance of high-speed SOCs is significantly hampered. We propose a partial core encryption methodology wherein the core vendor unveils only a small part of the core logic, successfully satisfying core IP protection requirements. Once the partially encrypted cores are merged into an SOC, the system integrator performs test generation on the visible SOC logic only, greatly reducing the test generation effort
doi:10.1109/iccad.2003.159675
fatcat:m3hnnpqlkjap7ewzfhlpomanuu