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Modelling the ARMv8 architecture, operationally: concurrency and ISA
2016
SIGPLAN notices
In this paper we develop semantics for key aspects of the ARMv8 multiprocessor architecture: the concurrency model and much of the 64-bit application-level instruction set (ISA). Our goal is to clarify what the range of architecturally allowable behaviour is, and thereby to support future work on formal verification, analysis, and testing of concurrent ARM software and hardware. Establishing such models with high confidence is intrinsically difficult: it involves capturing the vendor's
doi:10.1145/2914770.2837615
fatcat:nte3phwghzgllescf4xrg5rv4q