A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
PicoServer
2006
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems - ASPLOS-XII
In this paper, we show how 3D stacking technology can be used to implement a simple, low-power, high-performance chip multiprocessor suitable for throughput processing. Our proposed architecture, PicoServer, employs 3D technology to bond one die containing several simple slow processing cores to multiple DRAM dies sufficient for a primary memory. The 3D technology also enables wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be
doi:10.1145/1168857.1168873
dblp:conf/asplos/KgilDSBDMRF06
fatcat:didbkyujwfddjoviyhj6huxxum