Final Evaluation of MIPS M/500 Final Report for the RISC Insertion Project

Daniel V. Klein, Robert Firth
2018
In response to a request from the DoD, an analysis of a Reduced Instruction Set Computer (RISC) processor, the MIPS M/500, was performed. All aspects of processor capabilities and support software were evaluated, tested, and compared to familiar Complex Instruction Set Computer (CISC) architectures. In all cases, the RISC computer and its support software performed better than a comparable CISC computer. This report provides the general and specific results of these analyses, along with the
more » ... mmendation that the DoD and other government agencies seriously consider this or other RISC architectures as a highly viable and attractive alternative to the more familiar but less efficient CISC architectures.
doi:10.1184/r1/6573779 fatcat:cbsyk236znhpjirutowg2kpx64