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Final Evaluation of MIPS M/500 Final Report for the RISC Insertion Project
2018
In response to a request from the DoD, an analysis of a Reduced Instruction Set Computer (RISC) processor, the MIPS M/500, was performed. All aspects of processor capabilities and support software were evaluated, tested, and compared to familiar Complex Instruction Set Computer (CISC) architectures. In all cases, the RISC computer and its support software performed better than a comparable CISC computer. This report provides the general and specific results of these analyses, along with the
doi:10.1184/r1/6573779
fatcat:cbsyk236znhpjirutowg2kpx64