A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2012; you can also visit the original URL.
The file type is
Leakage power reduction of embedded memories on FPGAs through location assignment
Proceedings of the 43rd annual conference on Design automation - DAC '06
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already have a significant amount of memory on the die, and with each generation the proportion of embedded memory to logic cells is growing. While assigning high V th can limit the leakage power, embedded memory timing is critical to performance and will draw an increasingly significant amount of leakage current. However,doi:10.1145/1146909.1147067 dblp:conf/dac/MengSK06 fatcat:xw6vlkofx5gevhwj2fzn6m72ia