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Specifying and verifying hardware for tamper-resistant software
Proceedings 19th International Conference on Data Engineering (Cat. No.03CH37405)
We specify a hardware architecture that supports tamper-resistant software by identifying an "idealized" model, which gives the abstracted actions available to a single user program. This idealized model is compared to a concrete "actual" model that includes actions of an adversarial operating system. The architecture is verified by using a finite-state enumeration tool (a model checker) to compare executions of the idealized and actual models. In this approach, software tampering occurs if the
doi:10.1109/secpri.2003.1199335
dblp:conf/sp/LieMTH03
fatcat:iqfq527ayvbufidkdujw6lwvie