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Exploring SOI device structures and interconnect architectures for 3-dimensional integration
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
3-Dimensional (3-D) integration offers numerous advantages over conventional structures. Double-gate (DG) transistors can be fabricated for better device characteristics, and multiple device layers can be vertically stacked for better interconnect performance. In this paper, we explore the suitable device structures and interconnect architectures for multi-device-layer integrated circuits and study how 3-D SOI circuits can better meet the performance and power dissipation requirements projected
doi:10.1109/dac.2001.935623
fatcat:vgmj3qrom5azlnkigq53vekida