Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS

Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
2013 2013 23rd International Conference on Field programmable Logic and Applications  
Original Citation: Di Carlo S.; Gambardella G.; Indaco M.; Prinetto P.; Rolfo D.; Trotta P. (2013). Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS. ABSTRACT Thanks to their flexibility, FPGAs are nowadays widely used to implement digital systems' prototypes and, more frequently, their final releases. Reconfiguration traditionally required an external controller to upload contents in the FPGA. Dynamic Partial Reconfiguration (DPR) opens new horizons
more » ... in FPGAs' applications, providing many new utilization paradigms, as it enables an FPGA to reconfigure itself: no external controller is required since it can be included in the FPGA. However, DPR also introduces reliability issues related to errors in the partial reconfiguration bitstreams. FPGA manufacturers currently provide solutions that are not efficient. In this paper new DfD (Design for Dependability) techniques are proposed. Exploiting information density of configuration data, they improve the performance while providing the same reliability characteristics as the previous ones.
doi:10.1109/fpl.2013.6645549 dblp:conf/fpl/CarloGIPRT13 fatcat:bmovjl3a5jeivjfqf6khrlwcza