A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS
2013
2013 23rd International Conference on Field programmable Logic and Applications
Original Citation: Di Carlo S.; Gambardella G.; Indaco M.; Prinetto P.; Rolfo D.; Trotta P. (2013). Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS. ABSTRACT Thanks to their flexibility, FPGAs are nowadays widely used to implement digital systems' prototypes and, more frequently, their final releases. Reconfiguration traditionally required an external controller to upload contents in the FPGA. Dynamic Partial Reconfiguration (DPR) opens new horizons
doi:10.1109/fpl.2013.6645549
dblp:conf/fpl/CarloGIPRT13
fatcat:bmovjl3a5jeivjfqf6khrlwcza