FPGA-based high performance page layout segmentation

N.K. Ratha, A.K. Jain, D.T. Rover
Proceedings of the Sixth Great Lakes Symposium on VLSI  
doi:10.1109/glsv.1996.497588 dblp:conf/glvlsi/RathaJR96 fatcat:4zxliiaxrjhbfeekh4qns3gt6m