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At present, the main challenge for hardware implementation of turbo decoders is to achieve the high data rates required by current and future communication system standards. In order to address this challenge, a low complexity radix-16 SISO decoder for the Max-Log-MAP algorithm is proposed in this paper. Based on the elimination of parallel paths in the radix-16 trellis diagram, architectural solutions to reduce the hardware complexity of the different blocks of a SISO decoder are detailed.doi:10.1109/icecs.2012.6463718 dblp:conf/icecsys/SanchezJJS12 fatcat:2a3jsqspqvbcbe2n4pruer43lu