Design of Low Power 8-Bit Shift Register using PFF

2017 International Journal of Emerging Engineering Research and Technology  
In this brief, Design of low-power 8-bit shift register is done by using flip-flop (FF) design featuring an explicit type pulse-triggered structure based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Using 8-bits of PFF 8-Bit shift register is designed. Based on post-layout simulation results using TSMC CMOS
more » ... using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power delay product metrics are 22.7% and 29.7%, respectively. The objective of the project is to design 8-bit shift register using pulse triggered flip flop with signal feed through scheme which consumes less power and delay will be reduced. In this project different implicit and explicit type flip flops are simulated in Hspice using 180nm technology whereas proposed design circuit is simulated in Hspice using 90nm technology.
doi:10.22259/ijeert.0501005 fatcat:zdelodswrvbavft2r7d2wcmdqa