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A hybrid hardware/software approach to efficiently determine cache coherence Bottlenecks
2005
Proceedings of the 19th annual international conference on Supercomputing - ICS '05
High-end computing increasingly relies on shared-memory multiprocessors (SMPs), such as clusters of SMPs, nodes of chipmultiprocessors (CMP) or large-scale single-system image (SSI) SMPs. In such systems, performance is often affected by the sharing pattern of data within applications and its impact on cache coherence. Sharing patterns that result in frequent invalidations followed by subsequent coherence misses create cache coherence bottlenecks with significant performance penalties. Past
doi:10.1145/1088149.1088153
dblp:conf/ics/MaratheMS05
fatcat:6uraieljqbh7vjbfquvic3vanq