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Hardware acceleration of divide-and-conquer paradigms: a case study

W. Luk, V. Lok, I. Page
[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines  
We describe a method for speeding up divide-andconquer algorithms with a hardware coprocessor, using sorting as an example. The method employs a conventional processor for the "divide" and "merge" phases, while the "conquer" phase is handled by a purpose-built coprocessor. It is shown how transformation techniques from the Ruby language can be adopted in developing a family of systolic sorters, and how one of the resulting designs is prototyped in eight FPGAs on a PC coprocessor board known as
more » ... sor board known as CHS2x4 from Algotronix. The execution of the hardware unit is embedded in a sorting program, with the PC host merging the sorted sequences from the hardware sorter. The performance of this implementation is compared against various sorting algorithms on a number of PC systems. Partitioning strategy The first problem is to decide how the algorithm can be partitioned in two: one that will be implemented in
doi:10.1109/fpga.1993.279463 fatcat:2ni7d2ysajeptagamwllhhitl4