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Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Xiang Zhang, Jingwei Lu, Yang Liu, Chung-Kuan Cheng
2014 Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14  
We propose a prediction of the worst-case noise area of the supply voltage on the power distribution network (PDN). Previous works focus on the worst-peak droop to sign off PDN. In this work, we (1) study the behavior of circuit delay over the worst-area noise (2) study the worst-case noise area of a lumped PDN model (3) develop an algorithm to generate the worst-case current for general PDN cases (4) predict the longest delay of a datapath due to power integrity. Experimental results show that
more » ... l results show that the worst-area noise induces additional delay than that of the worst-peak noise. 1 D 0 ≈ 100ps according to our HSPICE simulation with 45nm PTM HP model [18] .
doi:10.1145/2633948.2633950 dblp:conf/slip/ChanKN14 fatcat:zx2lrx7eozf6xdyzoyiisg3ll4