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A highly-efficient technique for reducing soft errors in static CMOS circuits

S. Krishnamohan, N.R. Mahapatra
IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.  
Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Traditionally, they have been deemed to be a problem in memory structures, for which effective techniques (such as error correcting codes) are well known. However, due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic
more » ... gnitude in logic circuits. Existing circuit and architectural approaches to addressing soft errors in logic circuits have appreciable area/cost, performance, and/or energy overheads or are limited to particular types of circuits (combinational or sequential). We present a very efficient and systematic error masking technique that uses the same circuitry to cope with soft errors in combinational and sequential circuits. It prevents an SET pulse of width less than approximately half of the slack available in the propagation path from latching and turning into a soft error. The SET is masked without additional delay and within the clock cycle time in an area-and energy-efficient manner, which makes this technique attractive for commodity as well as reliabilitycritical applications. Our technique also tolerates soft errors in the overhead circuitry, which we minimize through clustering. Application of our technique to ISCAS85 benchmark circuits yields an average SER reduction of 70.93% with an average area overhead of only 11.98%. s12 s23 t s23¨¨¨¨¨¨¨© 1 2 t 3 t t
doi:10.1109/iccd.2004.1347911 dblp:conf/iccd/KrishnamohanM04 fatcat:4ddcrr43qfdbbontny3dotogmq