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PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists

R. Kuznar, F. Brglez
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)  
{ In this paper, we introduce a new recursive partitioning paradigm PROP which combines partitioning, replication, optimization, t o b e followed by another recursion of partitioning, etc. We measure the quality of partitions in terms of total device cost, logic and terminal utilization, and critical path delay. Traditionally, the minimum lower bound into which a given netlist can be p artitioned is determined b y disregarding the logic interconnect while distributing the logic nodes into a
more » ... ic nodes into a minimum number of devices. PROP paradigm challenges this assumption by demonstrating feasible partitions of some large netlists such that the number of device p artitions is smaller than minimum lower bounds postulated initially. Overall, we report consistent reductions in the total number of partitions for a wide range of combinational and sequential circuit benchmarks while, on the average, reducing critical path delay as well.
doi:10.1109/iccad.1995.480197 fatcat:p2seribhrjce5ekyt26sqpznxi