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Many digital communications algorithms present characteristics that make very difficult to implement them in either a software solution or as a fully custom hardware architecture. Their inherent complexity implies two challenges at the same time: to process the information as fast as possible to present the results when they are required, and to build a system that meets the power consumption and space constraints imposed by the application, while trying to maintain a low design intricacy. Thisdoi:10.1109/reconfig.2008.52 dblp:conf/reconfig/CampoCPO08 fatcat:xqwqo5lx6nh6hepfeakzcx6cuy