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We propose the "Multi-Split-Row" LDPC decoding method which allows further reductions in routing complexity, greater throughput, and smaller circuit area implementations compared to the previously proposed Split-Row decoding method. Multi-Split-Row is especially useful for regular high row weight LDPC codes. A 2048-bit full parallel decoder is implemented in a 0.18 µm CMOS technology using standard MinSum, Split-Row-2 and Split-Row-4 methods. The Split-Row-4 decoder delivers 7.1 Gbps throughputdoi:10.1109/icassp.2007.366160 dblp:conf/icassp/MohseninB07 fatcat:na2rhu3dfrdofpavtgjqsobqzi