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A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm2. The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect todoi:10.3390/electronics9030507 fatcat:kecjg747vbed5kf3eq7rdp2xmu