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Proceedings of the International Symposium on Low Power Electronics and Design
This paper presents a method of intra-task dynamic voltage scaling (DVS) for SoC design with hierarchical FSM and synchronous dataflow model (in short, HFSM-SDF model). To have an optimal intra-task DVS, exact execution paths need to be determined in compile time or runtime. In general programs, since determining exact execution paths in compile time or runtime is not possible, existing methods assume worst/average-case execution paths and take static voltage scaling approaches. In our work, wedoi:10.1109/lpe.2002.146716 fatcat:hjmssunfajca5dd3xyhgbx4wca