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Designing and Simulation of High Speed Area Efficient Full Adder Using Transmission Gates Logic

Swadesh Dubey, Dilip Ahirwar, Susmita Bilani, R Pandey, M-Tech Scholar
2017 International Journal of Engineering Technology and Applied Science   unpublished
Full Adder is the heart of any central processing unit that is a core component employed in all the processors. This thesis presents a design methodology using pass transistor logic and transmission gates for the architecture of full adder with minimum number of transistor i.e. reduced size and reduced delay. This is then used to implement a full adder design for carrying out arithmetic and logical tasks. The analysis of the developed full adder design is done at 27°C and 100°C range in CMOS 50
more » ... °C range in CMOS 50 nm technologies using Micro wind tool. The result shows the comparison between different CMOS technologies and temperature effect on the design in regards of delay in time and power dissipation. A comparison is also carried out by some of the parameters taking into consideration like delay of the proposed adder with existing full adder design, which shows the advantage of the full adder design. We are using different simulation tools like Micro-wind-DSCH and Questa-sim for waveform simulation. Firstly the adder cell will be implemented using DSCH tool. Then the Verilog code of the design is made and the layout will be made at CMOS 50 nm technology. The design will be simulated for both 27°C and 100°C temperature. We also use Questa-sim to simulate the full adder design. A comparison table will be shown having power, delay and transistor count based comparison at 50nm technologies showing delay in time and dissipated Power within the full adder design at both temperatures. We will also provide you the layout of the full adder design at both technologies.
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