A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is
This paper presents a new realization for a CMOS four-quadrant analogue multiplier. The proposed circuit is composed of three second generation current conveyor circuits (CCII), two NMOS transistors operating in the linear region, and four passive resistances. It can be operated in current mode and voltage mode without changing the circuit topology. The simulations results of the proposed mixed mode multiplier are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18doi:10.3906/elk-1708-179 fatcat:xj7fejcxbnb6lfswluullxuclm