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A hardware implementation of the Compact Genetic Algorithm

C. Aporntewan, P. Chongstitvatana
Proceedings of the 2001 Congress on Evolutionary Computation (IEEE Cat. No.01TH8546)  
We propose a hardware implementation of the Compact Genetic Algorithm (Compact GA). The design is realized using Verilog HDL, then fabricated on FPGA. Our design, though simple, runs about 1,000 times faster than the software executing on a workstation. An alternative hardware for linkage learning is also proposed in order to enhance the capability of Compact GA to solve highly deceptive problems. 0-7803-6657-3/01/$10.00
doi:10.1109/cec.2001.934449 fatcat:ouj2ctou2rdp7pi4igu3wnurjm